The present invention relates to a binary signal comparator circuit which may be used, for example, in the functional test of medium- and large-scale integrated circuits such as microprocessors and semiconductor memory devices and which may also be used in the test of assembled printed circuit boards. In such tests a comparator is used to compare an unknown binary signal with a reference signal during the entire duration of a predetermined time window. In one typical prior art functional tester having such a comparator (the Hewlett-Packard Company model 8182A Data Analyzer) the unknown and reference signals are connected to the inputs of an exclusive-OR gate. The exclusive-OR gate issues an error-indicating binary 1 comparison signal to a following AND gate if at any time the binary level of the unknown signal differs from the binary level of the reference signal. The AND gate is clocked open for the duration of the time window by a window signal and the AND gate generates a binary 1 error signal if a binary 1 compare signal is received at any time within the time window.
Unfortunately, the AND gates used in these prior art comparators have non-zero rise and fall times which are typically on tne order of 2-4 nanoseconds for ECL (emitter coupled logic) devices. In such prior art comparators 2-4 nanosecond uncertainty intervals exist at the beginning and at the end of the time window and in these uncertainty intervals a binary 1 compare signal may not be recognized because of the uncertain temporal overlap of the window and compare signals.
In accordance with the illustrated preferred embodiment of the present invention a binary signal comparator circuit operates with uncertainty intervals which are substantially reduced in duration from those in prior art comparators. An errorindicating binary 1 compare signal is generated, for example by an exclusive-OR gate, to indicate that the reference and unknown signals differ. The compare signal is monitored for the entire duration of the time window by a combination of two edgetriggered D-type flip-flops or equivalent bistable circuits. In such devices sampling is triggered by an edge of a clock signal and the delay between the clock signal edge and the sample time at which sampling actually occurs varies from sample to sample by a typical jitter amount in the range of only plus or minus 100 picoseconds. The first flip-flop is clocked by the rising edge of the window signal and stores the compare signal binary level then present. However, a binary 1 compare signal occuring later in time but still within the time window is not detected by the first flip-flop since no additional clock signal rising edge is available as a trigger. A second flip-flop is used to store such a later occuring binary 1 compare signal. The second flip-flop is triggered by the leading edge of the transition of the compare signal from a binary 0 to a binary 1 and stores the then current binary level of the window signal. The outputs of the two flip-flops may be combined logically in an OR gate so that a binary 1 error signal is provided if a binary 1 compare signal occurs at any time within the time window.